Cmos image sensor with noise cancellation

ABSTRACT

An image sensor having one or more pixels within a pixel array. A vertical signal line across the pixel array conductively connects to a drain terminal of a transistor of one of the pixels. The drain terminal is driven to a first drain voltage via the vertical signal line so that the transistor enters a triode region. A gate of the transistor is placed into a tri-state during the triode region, the gate being at a first gate voltage prior to the tri-state. The drain terminal is driven to a second drain voltage during the tri-state, whereby the gate is capacitively coupled to a second gate voltage. The second drain voltage may be higher than the first drain voltage so as to effectuate a gate voltage boosting for the transistor. The transistor may be a reset transistor having a drain terminal conductively coupled to reset said photodetector.

REFERENCE TO CROSS RELATED APPLICATION

This application claims priority under 35 U.S.C §119(e) to provisionalapplication No. 60/333,216, filed on Nov. 6, 2001; provisionalapplication No. 60/338,465, filed on Dec. 3, 2001 and provisionalapplication No. 60/345,672 filed on Jan. 5, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The subject matter disclosed generally relates to the field ofsemiconductor image sensors.

2. Background Information

Photographic equipment such as digital cameras and digital camcorderscontain electronic image sensors that capture light for processing intoa still or video image, respectively. There are two primary types ofelectronic image sensors, charge coupled devices (CCDs) andcomplimentary metal oxide semiconductor (CMOS) sensors. CCD imagesensors have relatively high signal to noise ratios (SNR) that providequality images. Additionally, CCDs can be fabricated to have pixelarrays that are relatively small while conforming with most camera andvideo resolution requirements. A pixel is the smallest discrete elementof an image. For these reasons, CCDs are used in most commerciallyavailable cameras and camcorders.

CMOS sensors are faster and consume less power than CCD devices.Additionally, CMOS fabrication processes are used to make many types ofintegrated circuits. Consequently, there is a greater abundance ofmanufacturing capacity for CMOS sensors than CCD sensors.

To date there has not been developed a CMOS sensor that has the same SNRand pixel pitch requirements as commercially available CCD sensors.Pixel pitch is the space between the centers of adjacent pixels. Itwould be desirable to provide a CMOS sensor that has relatively high SNRwhile providing a commercially acceptable pixel pitch.

CCD sensors contain pixel arrays that have multiple rows and columns.When capturing first and second images a CCD must read every row fromthe array for the first image and then every row in the array for thesecond image. This is a relatively inefficient approach that containsinherent delays in data retrieval. It would be desirable to decrease thetime required to retrieve data from the pixel array.

U.S. Pat. No. 5,587,728 issued to Shinohara describes an image sensorwith on-board memory. The memory stores signals from the pixel array.There are typically errors associated with storing and retrieving thesignals due to noise, drift, etc. The errors can produce invalid data.It would be desirable to provide an on-board memory for an image sensorthat does not require a zero noise margin.

BRIEF SUMMARY OF THE INVENTION

An image sensor with a control circuit that causes a pixel to provide areset output signal and a reference output signal.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic of an embodiment of an image sensor;

FIG. 2 is a schematic of an embodiment of a pixel of the image sensor;

FIG. 3 is a schematic of an embodiment of a light reader circuit of theimage sensor;

FIG. 4 is a schematic of an embodiment of a memory cell of the imagesensor;

FIG. 5 is a schematic of an embodiment of a storage writer circuit ofthe image sensor;

FIG. 6 is a schematic of an alternate embodiment of a storage writercircuit of the image sensor;

FIG. 7 is a schematic of an embodiment of a storage reader circuit ofthe image sensor;

FIG. 8 is a flowchart for a first mode of operation of the image sensor;

FIG. 9 is a timing diagram for the first mode of operation of the imagesensor;

FIG. 10 is a diagram showing the levels of a signal across a photodiodeof a pixel;

FIG. 11 is a schematic for a logic circuit for generating the timingdiagrams of FIG. 9;

FIG. 12 is a schematic of a logic circuit for generating a RST signalfor a row of pixels;

FIG. 13 is a timing diagram for the logic circuit shown in FIG. 12;

FIG. 14 is a flowchart showing a second mode of operation of the imagesensor;

FIG. 15 is a timing diagram for the second mode of operation of theimage sensor;

FIG. 16 is a flowchart showing a calibration routine for a digital toanalog converter of the image sensor;

FIG. 17 is a schematic of an alternate embodiment of the image sensor;

FIG. 18 is a schematic of a pixel of the image sensor shown in FIG. 17.

DETAILED DESCRIPTION

Disclosed is an image sensor that has one or more pixels within a pixelarray. The pixel array may be coupled to a control circuit and one ormore subtraction circuits. The control circuit may cause each pixel toprovide a first reference output signal and a reset output signal. Thecontrol circuit may then cause each pixel to provide a light responseoutput signal and a second reference output signal. The light responseoutput signal corresponds to the image that is to be captured by thesensor.

The subtraction circuit may provide a difference between the resetoutput signal and the first reference output signal to create a noisesignal that is stored in memory. The subtraction circuit may alsoprovide a difference between the light response output signal and thesecond reference output signal to create a normalized light responseoutput signal. The noise signal may then be subtracted from thenormalized light response output signal to generate the output data ofthe sensor. The second reference output signal is the same as the firstreference output signal so that the process in essence subtracts thereset noise from the light response signal.

This process increases the signal to noise ratio (SNR) of the sensor.The pixel may be a three transistor structure that minimizes the pixelpitch of the image sensor. The entire image sensor is preferablyconstructed with CMOS fabrication processes and circuits. The CMOS imagesensor has the characteristics of being fast, low power consumption,small pixel pitch and high SNR.

Referring to the drawings more particularly by reference numbers, FIG. 1shows an image sensor 10. The image sensor 10 includes a pixel array 12that contains a plurality of individual photodetecting pixels 14. Thepixels 14 are arranged in a two-dimensional array of rows and columns.

The pixel array 12 is coupled to a light reader circuit 16 by a bus 18and to a row decoder 20 by control lines 22. The row decoder 20 canselect an individual row of the pixel array 12. The light reader 16 canthen read specific discrete columns within the selected row. Together,the row decoder 20 and light reader 16 allow for the reading of anindividual pixel 14 in the array 12.

The light reader 16 may be coupled to an analog to digital converter 24(ADC) by output line(s) 26. The ADC 24 generates a digital bit stringthat corresponds to the amplitude of the signal provided by the lightreader 16 and the selected pixels 14.

The ADC 24 is connected to a digital to analog converter 28 (DAC) bybusses 30 and 32. The DAC 28 converts the digital bit string back to asingle pulse which has an amplitude dependent upon the value of the bitstring. The unit step size of the DAC 28 may be set by a referencecircuit 34.

The output of the DAC 28 is stored in a memory circuit 36 by a storagewriter circuit 38. The storage writer circuit 38 is connected to the DAC28 by output line(s) 40 and to memory 36 by a bus 42. The memory circuit36 may contain individual memory cells 44 that are each capable ofstoring multi-voltage levels.

The memory circuit 36 may be connected to the row decoder 20 by controlline(s) 46 that allow the decoder 20 to select individual rows of memorycells 44. The memory circuit 36 may be connected to a storage readercircuit 48 by a bus 50. The storage reader circuit 48 can readindividual columns of memory cells 44 located in a row selected by thedecoder 20.

The storage reader circuit 48 may be connected to an ADC 52 by controlline(s) 54. The ADC 52 generates a digital bit string in accordance withthe amplitude of the signal retrieved from memory 36. The ADC 52 may becoupled to a data combiner 56 by a bus 58. The combiner 56 may combinethe data on busses 32 and 58 onto an output bus 60. The data on bus 60may be provided to a processor (not shown). By way of example, thesensor 10 and processor may be integrated into photographic instrumentssuch as a digital camera, a digital camcorder, or a cellular phone unitthat contains a camera.

FIG. 2 shows an embodiment of a cell structure for a pixel 14 of thepixel array 12. The pixel 14 may contain a photodetector 100. By way ofexample, the photodetector 100 may be a photodiode. The photodetector100 may be connected to a reset transistor 112. The photodetector 100may also be coupled to a select transistor 114 through a level shiftingtransistor 116. The transistors 112, 114 and 116 may be field effecttransistors (FETs).

The gate of reset transistor 112 may be connected to a RST line 118. Thedrain node of the transistor 112 may be connected to IN line 120. Thegate of select transistor 114 may be connected to a SEL line 122. Thesource node of transistor 114 may be connected to an OUT line 124. TheRST 118 and SEL lines 122 may be common for an entire row of pixels inthe pixel array 12. Likewise, the IN 120 and OUT 124 lines may be commonfor an entire column of pixels in the pixel array 12. The RST line 118and SEL line 122 are connected to the row decoder 20 and are part of thecontrol lines 22.

FIG. 3 shows an embodiment of a light reader circuit 16. The lightreader 16 may include a plurality of double sampling capacitor circuits150 each connected to an OUT line 124 of the pixel array 12. Each doublesampling circuit 150 may include a first capacitor 152 and a secondcapacitor 154. The first capacitor 152 is coupled to the OUT line 124and ground GND1 156 by switches 158 and 160, respectively. The secondcapacitor 154 is coupled to the OUT line 124 and ground GND1 by switches162 and 164, respectively. Switches 158 and 160 are controlled by acontrol line SAMi 166. Switches 162 and 164 are controlled by a controlline SAM2 168. The capacitors 152 and 154 can be connected together toperform a voltage subtraction by closing switch 170. The switch 170 iscontrolled by a control line SUB 172.

The double sampling circuits 150 are connected to an operationalamplifier 180 by a plurality of first switches 182 and a plurality ofsecond switches 184. The amplifier 180 has a negative terminal − coupledto the first capacitors 152 by the first switches 182 and a positiveterminal + coupled to the second capacitors 154 by the second switches184. The operational amplifier 180 has a positive output + connected toan output line OP 188 and a negative output − connected to an outputline OM 186. The output lines 186 and 188 are connected to the ADC 24(see FIG. 1).

The operational amplifier 180 provides an amplified signal that is thedifference between the voltage stored in the first capacitor 152 and thevoltage stored in the second capacitor 154 of a sampling circuit 150connected to the amplifier 180. The gain of the amplifier 180 can bevaried by adjusting the variable capacitors 190. The variable capacitors190 may be discharged by closing a pair of switches 192. The switches192 may be connected to a corresponding control line (not shown).Although a single amplifier is shown and described, it is to beunderstood that more than one amplifier can be used in the light readercircuit 16.

FIG. 4 shows an embodiment of a single memory cell 44 of memory 36.Memory 36 has a plurality of memory cells 44 arranged within a twodimensional array that has both rows and columns. Each cell 44 mayinclude a first transistor 200, a second transistor 202 and a capacitor204. The gate of transistor 200 is connected to a WR control line 206.The drain of transistor 200 is connected to an input line SIN 208. Thesource of transistor 202 is connected to an output line SOUT 210.Capacitor 204 is connected to a RD control line 212, the source node oftransistor 200 and the gate of transistor 202. The WR 206 and RD 212control lines are connected to the row decoder 20 (see FIG. 1). Thecapacitor 204 stores the analog voltage level of a signal on line SIN208. The capacitor 204 may be a transistor with the drain and sourcenodes coupled together.

Converting the analog signal to a digital bit string and then back to ananalog signal creates a multi-level analog signal. The signal is“multi-level” because the stored analog signal has a level thatcorresponds to one of a number of discrete bit strings created by theADC 24. Storing a multi-level analog signal reduces the number of memorycells required to store the signals from the pixel array 14. Storingmulti-level analog signals also provides some immunity to small voltagelevel drift, particularly within the memory itself.

FIG. 5 shows an embodiment of a storage writer circuit 38 that writesinto the cells 44 of memory 36. The writer circuit 38 may include anamplifier 220 that is coupled to a plurality of column writer circuits222. The output of each column writer circuit 222 is connected to acorresponding input line SIN 208 of memory 36. Each column writer 222includes a first switch 224 that can couple a capacitor 226 to an outputof the amplifier 220 and a second switch 228 that can couple a negativeinput − of the amplifier to line SIN 208. The capacitor 226 is coupledto the line SIN 208 by a source follower transistor 230.

The positive terminal + of the amplifier 220 is connected to the outputline 40 of the DAC 28. The storage writer circuit 38 stores an analogoutput of DAC 28 plus the Vgs of source-follower FET 230 into thecapacitor 226 for later storage into memory 36. The switches 224 and 228are closed in a manner to sequentially store the analog outputs in thevarious column writers 222 of the storage writer circuit.

FIG. 6 shows an alternate embodiment wherein each column writer circuit222′ contains an amplifier 220 instead of one common amplifier as shownin FIG. 5.

FIG. 7 shows an embodiment of a storage reader circuit 48. The readercircuit 48 is similar to the light reader circuit 16. The reader circuit48 may include a plurality of double sampling capacitor circuits 240that are each connected to a SOUT line 210 of memory 36. Each doublesampling circuit 240 contains a first capacitor 242, a second capacitor244 and switches 246, 248, 250, 252 and 254. Switches 246 and 248 arecontrolled by a control line ESAM1 256. Switches 250 and 252 arecontrolled by a control line ESAM2 258. Switch 254 is controlled by acontrol line ESUB 260.

The double sampling circuits 240 are connected to an operationalamplifier 262 by a plurality of first switches 264 and a plurality ofsecond switches 266. The amplifier 262 has a positive terminal + coupledto the first capacitors 242 by the first switches 264 and a negativeterminal − coupled to the second capacitors 244 by the second switches266. The operational amplifier 262 has a positive output + connected toan output line EP 268 and a negative output − connected to an outputline EM 270. The output lines 268 and 270 are part of the control lines54 connected to the ADC 52 (see FIG. 1).

The operational amplifier 262 provides an amplified signal that is thedifference between the voltage stored in the first capacitor 242 and thevoltage stored in the second capacitor 244 of a sampling circuit 240connected to the amplifier 262. The capacitors 272 may be discharged byclosing the switches 274. The switches 274 may be connected to acorresponding control line (not shown). Although a single amplifier isshown and described, it is to be understood that more than one amplifiercan be used in the storage reader circuit 48.

FIGS. 8 and 9 show an operation of the image sensor 10 in a first modealso referred to as a low noise mode. In process block 300 a referencesignal is written into each pixel 14 of the pixel array and then a firstreference output signal is stored in the light reader. Referring toFIGS. 2 and 9, this can be accomplished by switching the RST 118 and IN120 lines from a low voltage to a high voltage to turn on transistor112. The RST line 118 is driven high for an entire row. IN line 120 isdriven high for an entire column. In the preferred embodiment, RST line118 is first driven high while the IN line 120 is initially low.

The RST line 118 may be connected to a tri-state buffer (not shown) thatis switched to a tri-state when the IN line 120 is switched to a highstate. This allows the gate voltage to float to a value that is higherthan the voltage on the IN line 120. This causes the transistor 112 toenter the triode region. In the triode region the voltage across thephotodiode 100 is approximately the same as the voltage on the IN line120. Generating a higher gate voltage allows the photodetector to bereset at a level close to Vdd. CMOS sensors of the prior art reset thephotodetector to a level of Vdd-Vgs, where Vgs can be up to 1 V.

During the reset operation, the reset transistor 112 is turned on whenthe RST signal is high and the IN signal (connected to drain node ofreset transistor 112) is also high. This allows a reset current to flowfrom the drain node to the source node of the reset transistor 112 underthe gate of the reset transistor 112. The reset current charges up thephotodiode 100, which is connected to the source node of the resettransistor 112.

The RST high voltage may be higher than one threshold voltage above theIN high voltage. In this case, the reset transistor 104 has a continuousinversion layer between the source and drain nodes that may flow ineither direction depending on the voltage difference between the sourceand the drain. In this case, the photodiode 100 is charged up to thesame voltage as the IN high voltage.

Alternatively, as is known in the art, the RST high voltage may be lowerthan one threshold voltage above the IN high voltage, and the inversionlayer below the gate of the reset transistor 104 is pinched off near thedrain node. In this case, the photodiode 100 is charged up toapproximately a voltage which is one threshold below RST high voltage.

The SEL line 122 is also switched to a high voltage level which turns ontransistor 114. The voltage of the photodiode 100 is provided to the OUTline 124 through level shifter transistor 116 and select transistor 114.The SAM1 control line 166 of the light reader 16 (see FIG. 3) isselected so that the voltage on the OUT line 124 is stored in the firstcapacitor 152.

Referring to FIG. 8, in process block 302 the pixels of the pixel arrayare then reset and reset output signals are then stored in the lightreader 16. Referring to FIGS. 2 and 9 this can be accomplished bydriving the RST line 118 low to turn off the transistor 112 and resetthe pixel 14. Turning off the transistor 112 will create reset noise,charge injection and clock feedthrough voltage that resides across thephotodiode 100. As shown in FIG. 10 the noise reduces the voltage at thephotodetector 100 when the transistor 112 is reset.

The SAM2 line 168 is driven high, the SEL line 122 is driven low andthen high again, so that a level shifted voltage of the photodiode 100is stored as a reset output signal in the second capacitor 154 of thelight reader circuit 16. Process blocks 300 and 302 are repeated foreach pixel 14 in the array 12.

Referring to FIG. 8, in process block 304 the reset output signals arethen subtracted from the first reference output signals to create noiseoutput signals that are then stored in memory 36. The noise outputsignals are provided to the ADC 24, DAC 28 and storage writer 38 forstorage into memory 36. Referring to FIGS. 2, 3, 4, 5 and 9, this can beaccomplished by closing switches 182, 184 and 170 of the light readercircuit 16 (FIG. 3) to subtract the voltage across the second capacitor154 from the voltage across the first capacitor 152.

The output of the amplifier 180 is converted to a digital bit string byADC 24 and then back to an analog signal by DAC 28. Switches 224 and 226of storage writer circuit 38 are closed and then opened to store thenoise signal into the capacitor 226.

To store the noise signal into memory the WR line 206 is driven high andthe RD line 212 is driven low to turn on transistor 200 of a memory cell44 (see FIG. 4). The voltage level of line SIN 208, which is the voltagestored in the capacitor 226 minus Vgs of transistor 230 of the storagewriter 38, is such that the transistor 200 operates in the trioderegion. This allows the capacitor 204 of memory cell 44 to charge to alevel that approximates the voltage stored in the capacitor 226 of thestorage writer circuit 38 minus the Vgs drop of transistor 230. WR line206 is then driven low to turn off the transistor 200.

Referring to FIG. 8, in block 306 light response output signals aresampled from the pixels 14 of the pixel array 12 and stored in the lightreader circuit 16. The light response output signals correspond to theoptical image that is being detected by the image sensor 10. Referringto FIGS. 2, 3 and 9 this can be accomplished by having the IN 120, SEL122 and SAM2 lines 168 in a high state and RST 118 in a low state. Thesecond capacitor 152 of the light reader circuit 16 stores a levelshifted voltage of the photodiode 100 as the light response outputsignal.

Referring to FIG. 8, in block 308 a second reference output signal isthen generated in the pixels 14 and stored in the light reader circuit16. Referring to FIGS. 2, 3 and 9, this can be accomplished similar togenerating and storing the first reference output signal. The RST line118 is first driven high and then into a tri-state. The IN line 120 isthen driven high to cause the transistor 112 to enter the triode regionso that the voltage across the photodiode 100 is the voltage on IN line120. The SEL 122 and SAM2 168 lines are then driven high to store thesecond reference output voltage in the first capacitor 154 of the lightreader circuit 16. Process blocks 306 and 308 are repeated for eachpixel 14 in the array 12.

Referring to FIG. 8, in block 310 the light response output signal issubtracted from the second reference output signal to create anormalized light response output signal. The normalized light responseoutput signal is converted into a digital bit string to create lightresponse data. Referring to FIGS. 2, 3 and 9 this can be accomplished byclosing switches 170, 182 and 184 of the light reader 16 to subtract thevoltage across the first capacitor 152 from the voltage across thesecond capacitor 154. The difference is then amplified by amplifier 180and converted into a digital bit string by ADC 24 as light responsedata.

Referring to FIG. 8, during the generation of the light response outputsignal, the storage reader circuit 48 reads data from memory 36 in block312. Referring to FIGS. 4, 7 and 9, this can be accomplished by enablingthe RD line 212 of a memory cell and then the ESAM1 line 256 of storagereader circuit 48 so that the noise signal stored in memory 36 isprovided to he first capacitor 242 of the storage reader 48.

A storage reference signal is read from the DAC 28, stored in a memorycell 44 and then stored in the second capacitor 244 of the storagereader 48. The voltage across capacitors 242 and 244 are subtracted tocreate a normalized analog noise signal. The storage reference signalmay be the lowest value of the DAC 28 and is subtracted from the storedanalog signal to compensate for errors created by the storagewrite-and-read process.

The ADC 52 converts the normalized analog noise signal into a digitalbit string that will be referred to as noise data. Storing the noisesignal as a multi-level signal and converting the normalized analognoise signal into discrete digitized levels immunizes the storage andretrieval process from small noise and level drift.

Referring to FIG. 8, in block 314 the combiner 56 subtracts the noisedata from the normalized light response data to create image data. Thesecond reference output signal is the same or approximately the same asthe first reference output signal such that the present techniquesubtracts the noise data, due to reset noise, charge injection and clockfeedthrough, from the normalized light response-signal. This improvesthe signal to noise ratio of the final image data. The image sensorperforms this noise cancellation with a pixel that has only threetransistor. This image sensor thus provides noise cancellation whilemaintaining a relatively small pixel pitch.

The process described is performed in a sequence across the various rowsof the pixels in the pixel array 12 and the memory cells of memory 36.As shown in FIG. 9, the n-th row in the pixel array may be generatingnoise signals while the n-l-th row generates normalized light responsesignals, where 1 is the exposure duration in multiples of a line period.

The various control signals RST, SEL, IN, SAM1, SAM2, SUB, RD, WR,ESAM1, ESAM2, ESUB can be generated in the circuit generally referred toas the row decoder 20. FIG. 11 shows an embodiment of logic to generatethe IN, SEL, SAM1, SAM2 and RST signals in accordance with the timingdiagram of FIG. 9. The logic may include a plurality of comparators 350with one input connected to a counter 352 and another input connected tohardwired signals that contain a lower count value and an upper countvalue. The counter 352 sequentially generates a count. The comparators350 compare the present count with the lower and upper count values. Ifthe present count is between the lower and upper count values thecomparators 350 output a logical 1.

The comparators 350 are connected to plurality of AND gates 356 and ORgates 358. The OR gates 358 are connected to latches 360. The latches360 provide the corresponding IN, SEL, SAM1, SAM2 and RST signals. TheAND gates 356 are also connected to a mode line 364. To operate inaccordance with the timing diagram shown in FIG. 9, the mode line 364 isset at a logic 1.

The latches 360 switch between a logic 0 and a logic 1 in accordancewith the logic established by the AND gates 356, OR gates 358,comparators 350 and the present count of the counter 352. For example,the hardwired signals for the comparator coupled to the IN latch maycontain a count value of 6 and a count value of 24. If the count fromthe counter is greater or equal to 6 but less than 24 the comparator 350will provide a logic 1 that will cause the IN latch 360 to output alogic 1. The lower and upper count values establish the sequence andduration of the pulses shown in FIG. 9. The mode line 364 can beswitched to a logic 0 which causes the image sensor to function in asecond mode.

The sensor 10 may have a plurality of reset RST(n) drivers 370, eachdriver 370 being connected to a row of pixels. FIGS. 12 and 13 show anexemplary driver circuit 370 and the operation of the circuit 370. Eachdriver 370 may have a pair of NOR gates 372 that are connected to theRST and SAM1 latches shown in FIG. 11. The NOR gates control the stateof a tri-state buffer 374. The tri-state buffer 374 is connected to thereset transistors in a row of pixels. The input of the tri-state bufferis connected to an AND gate 376 that is connected to the RST latch and arow enable ROWEN(n) line.

FIGS. 14 and 15 show operation of the image sensor in a second mode alsoreferred to as an extended dynamic range mode. In this mode the imageprovides a sufficient amount of optical energy so that the SNR isadequate even without the noise cancellation technique described inFIGS. 8 and 9. Although it is to be understood that the noisecancellation technique shown in FIGS. 8 and 9 can be utilized while theimage sensor 10 is in the extended dynamic range mode. The extendeddynamic mode has both a short exposure period and a long exposureperiod. Referring to FIG. 12, in block 400 each pixel 14 is reset tostart a short exposure period. The mode of the image sensor can be setby an external circuit such as a processor that determines whether thesensor should be in the low noise mode, or the extended dynamic rangemode.

In block 402 a short exposure output signal is generated in the selectedpixel and stored in the second capacitor 154 of the light reader circuit16. The level shifted voltage of the photodiode 100 is stored in thefirst capacitor 152 of the light reader circuit 16 as a reset outputsignal. In block 404 each pixel is again reset to start a long exposureperiod.

In block 404 each reset transistor is reset and the short exposureoutput signal is subtracted from the reset output signal in the lightreader circuit 16. The difference between the short exposure signal andthe reset signal is converted into a binary bit string by ADC 24. TheDAC 28 and storage writer circuit 38 convert M MSB bits of the ADCoutput into an analog storage signal having one of 2″ discrete levels.The short exposure analog signal is stored into memory 36.

In block 406 the light reader circuit 16 stores a long exposure outputsignal from the pixel in the second capacitor 154. In block 408 thepixel is reset and the light reader circuit 16 stores the reset outputsignal in the first capacitor 152. The long exposure output signal issubtracted from the reset output signal, amplified and converted into abinary bit string by ADC 24 as long exposure data.

The storage reader 48 begins to read the short exposure analog signalsfrom memory 36 while the light reader 16 reads the long exposure signalsfrom the pixel array in block 410. The short exposure analog signals areconverted into a binary bit string by ADC 52 into short exposure data.

The combiner 56 may append the short exposure data to the long exposuredata in block 412. The number of bits from the short exposure dataappended to the long exposure data may be dependent upon the exposuretimes for the long and short exposures. By way of example, log₂(l) mostsignificant bits (MSB) of the short exposure data may be appended to thelong exposure data, where l is the time ratio of long to shortexposures. The ratio l should not exceed 2^(M−1) where M is the numberof bits to be stored in memory for short exposure data from each pixel.For example, if l is equal to 16 and M is equal to 10 then the retrievedshort-exposure data is right-extended with 4 bits of zeros and thelong-exposure data left-extended with 4 bits of zeros. The final outputis 14 bits and is selected from the left-extended long-exposure data ifthe value of the long-exposure data is less than 512, otherwise theoutput is the right-extended short-exposure data. This technique extendsthe dynamic range by log₂(l).

FIG. 15 shows the timing of data generation and retrieval for the longand short exposure data. The reading of output signals from the pixelarray 12 overlap with the retrieval of signals from memory 36. Shortexposure data is retrieved from memory before the long exposure periodhas ended. FIG. 15 shows timing of data generation and retrieval whereina n-th row of pixels starts a short exposure, the (n-k)-th row ends theshort exposure period and starts the long exposure period, and the(n-k-l)-th row of pixels ends the long exposure period. Where k is theshort exposure duration in multiples of the line period, and l is thelong exposure duration in multiples of the line period. The short andlong exposure output signals are retrieved from the rows of the pixelarray in an interleaved manner.

The storage reader circuit 48 and ADC 52 begin to retrieve shortexposure data for the pixels in row (n-k-l) at the same time as the(n-k-l)-th pixel array is completing the long exposure period. Thisshown by the enablement of control signals ESAM1, ESAM2 and RD(n-k-l).At the beginning of a line period, the light reader circuit 16 retrievesthe short exposure output signals from the (n-k)-th row of the pixelarray 12 as shown by the enablement of signals SAM1, SAM2, SEL(n-k) andRST(n-k). The light reader circuit 16 then retrieves the long exposuredata of the (n-k-l)-th row.

The output of the combiner 56 can be provided to an off-board processorsuch as a DSP (not shown). The processor may first analyze the imagewith the long exposure data. The photodiodes may be saturated if theimage is too bright. This would normally result in a “washed out” image.The processor can process the long exposure data to determine whetherthe image is washed out, if so, the processor can then use the shortexposure image data. The processor can also use both the long and shortexposure data to compensate for saturated portions of the detectedimage.

Although a process is described as performing discrimination between theshort and long exposure data, it is to be understood that the combiner56 may include logic that determines whether to append the shortexposure data to the long exposure data. For example, the combiner 56may append all logic zeros to the long exposure data if the longexposure data is below a threshold.

Although an extended dynamic range mode is described, wherein a shortexposure is followed by a long exposure, it is to be understood that theprocess may include a long exposure followed by a short exposure. Theretrieved long exposure data are left-extended by log₂(l) bits of zerosand the short exposure data right-extended by log₂(l) bits of zeros, andthe extended long-exposure data replaces the extended short-exposuredata if the value of the extended long-exposure data is less than2^(M−1) For Example, assume an exposure ratio of l=16 and M=10, and the1^(st) ADC output is 10 bits. The 10 bit long-exposure data retrievedfrom memory is left-extended by 4 bits of zeros to make a 14-bitextended long-exposure data. At the same time the 10-bit short exposuredata is right-extended by 4 bits of zeros. The 14-bit short-exposuredata is then replaced by the 14 bit long-exposure data if the value ofthe 14-bit long-exposure data is less than 512.

The dual modes of the image sensor 10 can compensate for varyingbrightness in the image. When the image brightness is low the outputsignals from the pixels are relatively low. This would normally reducethe SNR of the resultant data provided by the sensor, assuming theaverage noise is relatively constant. The noise compensation schemeshown in FIGS. 8 and 9 improve the SNR of the output data so that theimage sensor provides a quality picture even when the subject image isrelatively dark. Conversely, when the subject image is too bright theextended dynamic range mode depicted in FIGS. 12 and 13 compensates forsuch brightness to provide a quality image.

The signal retrieved by the storage reader 48 may be attenuated from thesignal output by DAC 28, causing retrieved data to be smaller thanoriginal written data. This can be compensated by making the step sizeof the DAC 28 larger than the step size of the ADC 52. The step size ofthe DAC 28 can be varied by adjusting the reference circuit 34.

FIG. 16 shows a calibration routine for adjusting the DAC 28 during apower up routine. In block 450 the reference circuit 34 is set to thelowest output level so that the 2^(M−2) output of the DAC 28 is at thelowest possible level. The 2^(M−2) output level of the DAC 28 is storedin memory 36 and then retrieved from memory in blocks 452 and 454. Theretrieved signals are converted into binary form and then averaged inblock 456. The average value is then compared with the 2^(M−2) output ofDAC 28 in decision block 458. If the average value is less than 2^(M)−2then the value within the reference 34 is incremented one unit in block460 and the process is repeated. The process repeats until the averageis not less than the 2^(M)−2 output wherein the calibration process iscompleted.

FIGS. 17 and 18 show an alternate embodiment of an image sensor 10′wherein the memory cells 44 are located within each pixel 14′ of thepixel array 12′. The entire sensor 10′ may be constructed with CMOSfabrication processes. Such an arrangement may reduce the overall diesize of the image sensor 10′. This construction may be undesirable ifthe inclusion of the memory cells 44 increases the pixel size to anundesirable value.

It is the intention of the inventor that only claims which contain theterm “means” shall be construed under 35 U.S.C. §112, sixth paragraph.

While certain exemplary embodiments have been described and shown in theaccompanying drawings, it is to be understood that such embodiments aremerely illustrative of and not restrictive on the broad invention, andthat this invention not be limited to the specific constructions andarrangements shown and described, since various other modifications mayoccur to those ordinarily skilled in the art.

The elements 12, 16, 20, 24, 28, 34, 36, 38, 48, 52 and 56 shown in FIG.1 may all be integrated onto a single integrated circuit. As alternateembodiments on or more of the elements may be located on a differentintegrated circuits.

Additionally, the memory 36 may have more or less cells and lines thanthe pixel array 12. For example, memory may use 3 storage cells per 2pixels if a storage cell can store 64 levels (8 bits) and a pixel outputis 12 bits. Likewise, fewer lines of memory are needed for an imagesensor with only the extend dynamic range mode and the short exposureperiod is subsequent to the long exposure period.

1. A method for changing a gate voltage of a gate of a transistor in apixel array of an image sensor, the transistor coupled to aphotodetector in said pixel array, a vertical signal line across saidpixel array coupled to transmit a voltage signal to a drain terminal ofsaid transistor, comprising: driving said drain terminal to a firstdrain voltage via said vertical signal line so that said transistorenters a triode region; placing said gate into a tri-state during saidtriode region, said gate being at a first gate voltage prior to saidtri-state; and driving said drain terminal to a second drain voltageduring said tri-state, whereby said gate is capacitively coupled to asecond gate voltage.
 2. The method of claim 1, wherein said second drainvoltage is higher than said first drain voltage and said second gatevoltage is higher than said first gate voltage.
 3. The method of claim1, wherein said placing of said gate into a tri-state is by switchingoff a driving of a circuit, said circuit otherwise can output a currentto said gate.
 4. The method of claim 1, wherein said transistor is areset transistor and said drain terminal is conductively coupled toreset said photodetector.
 5. The method of claim 1, wherein saidvertical signal line is an IN line.
 6. The method of claim 1, whereinsaid drain terminal is driven to said first drain voltage via a sourceterminal of said transistor.
 7. The method of claim 2, wherein a sourceterminal of said transistor has a voltage rise during said tri-state,whereby said gate is capacitively coupled from said source terminal. 8.The method of claim 2, wherein a channel of said transistor has avoltage rise during said tri-state, whereby said gate is capacitivelycoupled from said channel.
 9. The method of claim 1, wherein said seconddrain voltage is a predetermined voltage.